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1 low power audio codec features system ? high performance and low power multi - bit delta - sigma audio adc and dac ? i 2 s/pcm master or slave serial data port ? two pair s of analog input with differential input option ? 256 /384fs and u sb 12/ 24 mhz system clocks ? sophisticated analog input and output routing, mixing and gain ? i 2 c interface adc ? 24- bit, 8 to 96 khz sampling frequency ? 9 2 db signal to noise ratio, - 85 db thd+n ? low noise pre - amplifier ? auto level control (alc) and noise gate ? mic bias ? support digital mic dac ? 24- bit, 8 to 96 khz sampling frequency ? 9 3 db signal to noise ratio, - 85 db thd+n ? ground centered h eadphone driver ? 3 - band peq ? stereo enhancement ? headphone and external mic detection ? pop and click noise suppression low power ? 1.8v to 3.3v operation ? 7 mw playback; 16 mw playback and record a pplications ? mid/tablet ? wireless audio ? portable audio o rdering i nformation ES8316 -40 c ~ +85 c qfn - 32 ES8316
everest semiconductor confidential ES8316 revision 6 .0 2 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 1. block diagram cpvdd cpgnd cptop cpbot cpvssp cpgndref dvdd pvdd dgnd avdd agnd adcvref dacvref vmid micbias mclk cdata cclk ce gpio1 gpio2 gpio3 dsdin asdout sclk dlrck lin2 lin1 rin1 rin2 i 2 c gpio mic bias pga mixer hp driver power supply i 2 s/pcm adc alc dac peq dac se stereo dac rout mono adc analog reference pga mixer hp driver lout lin1 lin2 rin2 rin1 clock mgr charge pump pga 1 pga 2
everest semiconductor confidential ES8316 revision 6 .0 3 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 2. pin out and description pin name i/o description 1 cclk i i 2 c clock input 2 mclk i master clock 3 dvdd supply digital core supply 4 p vdd supply digital io supply 5 dgnd supply digital ground 6 s clk i/o audio data bit clock 7 dsdin i dac audio data 8 d lrck i/o dac a udio data left and right clock 9 asdo ut o adc audio data 10 gpio1 i/o general purpose io 11 gpio2 i/o general purpose io 1 2 gpio 3 i/o general purpose io 13 cpvssp charge pump filtering 14 cpvdd charge pump power supply 15 cptop charge pump capacitor top 16 cpbot charge pump capacitor bottom 17 cpgnd charge pump ground 18 cpgndref charge pump filtering 19 rout o right analog output 20 lout o left analog output 21 dac vref o d ecoupling capacitor 22 avdd supply analog supply 23 agnd supply analog ground 24 adc vref o d ecoupling capacitor 25 vmid o d ecoupling capacitor 26 micbias o mic bias 27 rin 2 i right analog input 2 8 lin 2 i left analog input 29 rin1 i right analog input 30 lin1 i left analog input 31 ce i i 2 c d evice address selection 32 cdata i/o i 2 c data input or output ES8316 cclk mclk dvdd pvdd dgnd sclk dsdin dlrck 1 2 3 4 5 6 7 8 adcvref agnd avdd dacvref lout rout cpgndref cpgnd 24 23 22 21 20 19 18 17 vmid micbias rin2 lin2 rin1 lin1 ce cdata 25 26 27 28 29 30 31 32 cpbot cptop cpvdd cpvssp gpio3 gpio2 gpio1 asdout 16 15 14 13 12 11 10 9
everest semiconductor confidential ES8316 revision 6 .0 4 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 3. typical application circuit dvdd p vd d 0.1uf 0.1uf 1uf cpu/dsp agnd agnd agnd agnd 0r gnd(sys) * mi cb ias lin 2 28 cc lk 1 m c lk 2 p vd d 4 dgnd 5 dsi n 7 lrc k 8 adsout 9 gpio1 10 cpvssp 13 gpio3 12 gpio2 11 cpg nd 17 cpgndref 18 hpr 19 hpl 20 dacvref 21 vdda 22 gnda 23 adcvref 24 vmid 25 micbias 26 ri n2 27 dvdd 3 cpv dd 14 cpp 15 cpn 16 sclk 6 cd ata 32 ri n1 29 lin 1 30 ce0 31 pgnd 33 ES8316 ever es t 1uf 1uf agnd * 1uf * 1uf * * 1uf 1uf 1uf 1uf mic1p mic1n mic2p mic2n 1uf agnd avdd cpvdd-1v8 * 1uf * 1uf * agnd agnd agnd 10k 8 mic 1 6 ro ut 3 4 lout 5 gnd 2 7 hp _ct ia hp-inset hp- mic p vd d 33r 33r pin18 must be connected to the agnd junction on hp in the layout, chip is treated as an analog device for the best performance,decoupling and filtering capacitors should be located as close to the device package as possible additional parallel capacitors(typically 0.1 f) can be used, larger value capacitors (typically 10 f) would also help * *
everest semiconductor confidential ES8316 revision 6 .0 5 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 4. clock modes and samp ling frequencies the device supports two types of clocking: standard audio clocks (256fs, 384fs, 512fs, etc), and usb clocks (12/24 mhz) . according to the serial audio data sampling frequency (fs) , the device can work in two speed modes : single speed mode or double speed mode. in single speed mode, fs normally ranges from 8 khz to 48 khz, and in double speed mode, fs normally range from 64 khz to 96 khz. the device can work e ither in master clock mode or slave clock mode. in slave mode, lrck and sclk are supplied externally, and lrck and sclk must be synchronously derived from the system clock with specific rates. in master mode, lrck and sclk are derived internally from devic e master clock. 5. micro - controller configura tion interface the device supports standard i 2 c micro - controller configuration interface. external micro - controller can completely configure the device through writing to in ternal configuration registers. i 2 c inter face is a bi - directional serial bus that uses a serial data line (sda) and a serial clock line (scl) for data transfer. the timing diagram for data transfer of this interface is given in figure 1 . data are transmitted synchronously to scl clock on the sda line on a byte - by - byte basis. each bit in a byte is sampled during scl high with msb bit being transmitted firstly. each transferred byte is followed by an acknowledge bit from receiver to pull the sda low. the transfer rate of this interface can be up to 4 00 k bps. figure 1 data transfer for i 2 c interface a master controller initiates the transmission by sending a start signal, which is defined as a high - to - low transition at sda while scl is high. the first byte transferred is the slave address. it is a seven - bit chip address followed by a rw bit. the chip address must be 0010 00x, where x equals ad0 . the rw bit indicates the slave data transfer direction. once an acknowledge bit is received, the data transfer starts to proceed on a byte - by - byte basis in the direction specified by the rw bit. the master can terminate the communication by generating a stop signal, which is defined as a low -to - high transition at sda while scl is high.
everest semiconductor confidential ES8316 revision 6 .0 6 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com in i 2 c interface mode, the registers can be written and read. the format s of write and read instructions are shown in table 1 and table 2 . please note that, to read data from a register, you must set r/w bit to 0 to access the register address and then set r/w to 1 to read data from the register. table 1 write data to regi ster in i 2 c interface mode chip address r/w register address data to be written 001000 ad0 0 ack ram ack data table 2 read data from register in i 2 c interface mode chip address r/w register address 001000 ad0 0 ack ram chip address r/w data to be read 001000 ad0 1 ack data 6. digital audio interf ace the device provides many formats of serial audio data interface to the input of the dac or out put from the adc through lrck, b c lk (sclk) and dacdat/adcdat pins. these formats are i 2 s, left justified, dsp/pcm and tdm mode. dac input dacdat is sampled by the device on the rising edge of sclk. adc data is out at adcdat on the falling edge of sclk. the relationship of sdata (dacdat/adcdat ), sclk and lrck with these formats are shown through figure 2 to fig ure 6 . n-2 n-1 n 3 2 1 1 n-2 n-1 n 3 2 1 1 figure 2 i 2 s serial audio data format up to 24 - bit n-2 n-1 n 3 2 1 n-2 n-1 n 3 2 1 figure 3 left justified serial audio data format up to 24 - bit
everest semiconductor confidential ES8316 revision 6 .0 7 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com figure 5 dsp/pcm mode a figure 6 dsp/pcm mode b 7. electrical character istics absolute maximum rat ings continuous operation at or beyond these conditions may permanently damage the device. parameter min max analog supply voltage level - 0.3v +5.0v digital supply voltage level - 0.3v +5.0v input voltage r ange dgnd - 0.3v dvdd+0.3v operating temperature range -40 c +85 c storage temperature -65 c +150 c recommended operatin g conditions parameter min typ max unit avdd 2.0 3.3 3.6 v cpvdd 1.6 1.8 2.0 v dvdd 1.6 1.8 3.6 v pvdd 1. 6 1.8 3.6 v
everest semiconductor confidential ES8316 revision 6 .0 8 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com adc analog and filte r characteristics and specifications test conditions are as the following unless otherwise specify: avdd= 3.3v, d cvdd= 1.8v, agnd=0v , dgnd=0v, ambient temperature= 25 c, fs=48 khz, 96 khz or 192 khz, mclk/lrck=256. parameter min typ max unit adc performance signal to noise ratio (a - weigh) 85 92 95 db thd+n -88 -85 -75 db channel separation (1khz) 80 85 90 db interchannel gain mismatch 0.1 db gain error 5 % filter frequency response C single speed passband 0 0.4535 fs stopband 0.5465 fs passband ripple 0.05 db stopband attenuation 50 db filter frequency response C double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 50 db analog input full scale input level avdd/3.3 vrms input impedance 20 k dac analog and filte r characteristics an d specifications test conditions are as the following unless otherwise specify: avdd=3.3v, dcvdd=1.8v, agnd=0v, dgnd=0v, ambient temperature=25 c, fs=48 khz, 96 khz or 192 khz, mclk/lrck=256. param eter min typ max unit dac performance signal to noise ratio (a - weigh) 83 9 3 9 5 db thd+n - 85 - 83 - 75 db channel separation (1khz) 80 85 90 db interchannel gain mismatch 0.05 db filter frequency response C single speed passband 0 0.4535 fs stopband 0.5465 fs passband ripple 0.05 db stopband attenuation 40 db filter frequency response C double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db
everest semiconductor confidential ES8316 revision 6 .0 9 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com stopband attenuation 40 db de - emphasis error at 1 khz (single speed mode only) fs = 32khz fs = 44.1khz fs = 48khz 0.002 0.013 0.0009 db analog output full scale output level avdd/3.3 vrms power consumption ch aracteristics parameter min typ max unit normal operation mode dvdd=1.8v, pvdd=1.8v, avdd=1.8v: play back play back and record dvdd=3.3v, pvdd=3.3v, avdd=3.3v: play back play back and record 7 16 31 59 mw power down mode dvdd=1.8v, pvdd=1.8v, avdd=1.8v dvdd=3.3v, pvdd=3.3v, avdd=3.3v tbd tbd mw serial audio port sw itching specifications parameter symbol min max unit mclk frequency 51.2 mhz mclk duty cycle 40 60 % lrck frequency 200 khz lrck duty cycle 40 60 % sclk frequency 26 mhz sclk pulse width low tsclkl 15 ns sclk pulse width high tsclkh 15 ns sclk falling to lrck edge tslr C 10 10 ns sclk falling to sdout valid tsdo 0 ns sdin valid to sclk rising setup time tsdis 10 ns sclk rising to sdin hold time tsdih 10 ns
everest semiconductor confidential ES8316 revision 6 .0 10 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com figure 8 serial audio port timing i 2 c switching specificat ions parameter symbol min max unit scl clock frequency f scl 400 khz bus free time between transmissions t twid 1.3 us start condition hold time t twsth 0.6 us clock low time t twcl 1.3 us clock high time t twch 0.4 us setup time for repeated start condition t twsts 0.6 us sda hold time from scl falling t twdh 900 ns sda setup time to scl rising t twds 100 ns rise time of scl t twr 300 ns fall time scl t twf 300 ns s p sda scl t twsts t twsth t twch t twcl t twdh t twds t twf t twr s t twid figure 10 i 2 c timing
everest semiconductor confidential ES8316 revision 6 .0 11 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 8. package
everest semiconductor confidential ES8316 revision 6 .0 12 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 9. corpo rate information everest semiconductor co., ltd. ????? 1355 ???? , ? 215021 email: info@everest - semi.com

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